好的操作系统

C51编写的SST s操作FLASH源代码，用单片机操作为SST39VF040

模拟串口，点阵显示固定八字，51单片机平台-Serial simulation, a fixed eight-character dot matrix display, 51 single-chip platform! ! !

ARM里实现 PWM ARM经典 C语言写的-ARM achieve PWM

自己的51实习是做得数字时钟，可以调整时间，可以显示当前温度。-51 is doing his internship digital clock, you can adjust the time, you can display the current temperature.

89c51的isp下载程序C语言版源代码。可无编程器在线编程。-89c51 isp download the C language version of the source code. Programming can be no on-line programming.

《模拟I2C总线多主通信的通用软件包》,支持多主竞争，比如有多个单片机和I2C器件同时工作。- Simulation of multi-master I2C bus communications generic package to support multi-master competition, for example, has a number of SCM and I2C devices work at the same time.

用单片机驱动驱动液晶显示器，实现计时，测温等功能的 开发环境为keil-Using single-chip LCD driver drive, realize the time, temperature and other functions of the development environment for keil

用485实现单片机之间的串行通信。 从机部分一直等待主机的命令，接收到就发响应信号，然后接受数据，接受成功就用液晶显示-MCU with 485 Serial Communication between. From the plane of the mainframe have been waiting for the orders received on the response signal and then receive data on the successful use of acceptable LCD

small rtos for avr small rtos 使用了动态堆栈 想无需任何改动就可以编译这个程序，就必须安装winavr20050214和uv2,先点击uv2的工程文件打开这个工程然后在Tools---->Customize Tools Menu...嵌入gcc编译命令make all和make clean即可立即编译。编译后可以使用avr studio进行代码级仿真-small Byelorussian for avr small Byelorussian use of dynamic stack without any changes to be compiled for the process, it must be installed and uv2 winavr20050214, first click uv2 works documents before the project opened in Tools- gt; Customize Tools Menu ... embedded gcc compiler make all orders and instantly make clean compile. Compiled avr studio can be used for code-level simulation

本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。-The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to SPCE061A Singlechip for process control and scheduling core mission FPGA for external expansion, internal self-system bus, address decoding using the entire translated code approach. DDS has built internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal.