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an overvalued on VBA books, AutoCad is a rare open secondary development.
一本超值讲解VBA开发的书籍,属于难得的AutoCad开二次开发。-an overvalued on VBA books, AutoCad is a rare open secondary development.
- 2022-09-25 19:40:03下载
- 积分:1
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vc++ 技术内幕(第四版),听说一般,不过也是大师写的
vc++ 技术内幕(第四版),听说一般,不过也是大师写的-vc Technology Insider (fourth), I heard that the general, but also to write the master
- 2022-10-25 05:50:03下载
- 积分:1
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redhat服务器安装配置和开发指南,包括fedora
redhat服务器安装配置和开发指南,包括fedora-redhat server installation configuration and development of guidelines, including the fedora
- 2023-02-14 21:05:04下载
- 积分:1
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一本很好的管理电子书
一本很好的管理电子书-a well managed e-books
- 2022-02-27 06:31:47下载
- 积分:1
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水泵性能参数检测是水泵出厂检验与开发研究的必要手段,传统的检测系统存在硬件集成复杂,人机交互性能差,操作不方便等缺点...
水泵性能参数检测是水泵出厂检验与开发研究的必要手段,传统的检测系统存在硬件集成复杂,人机交互性能差,操作不方便等缺点-Detection of pump performance parameters is the factory tested pump research and development of the necessary means, the traditional hardware integration testing of complex systems, poor performance of human-computer interaction, such as the shortcomings of the operation is not convenient
- 2022-03-06 11:58:29下载
- 积分:1
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很好的用Visual Basic完成了PC机与RS232之间的通信,具有就很好的参考价值...
很好的用Visual Basic完成了PC机与RS232之间的通信,具有就很好的参考价值-Very good use of Visual Basic completed between PC computer and RS232 communications, with a good reference value
- 2022-04-08 08:07:21下载
- 积分:1
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8051 programming. Singlechip introduce the basic foundation of knowledge, very u...
8051单片机程序设计.介绍基本的单片机基础知识,非常实用-8051 programming. Singlechip introduce the basic foundation of knowledge, very useful
- 2023-08-15 22:50:03下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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Practice and application of single
8051单片机在MCS-51单片机上的实践与应用&以中国水利水电出版社为例
- 2023-03-12 00:30:04下载
- 积分:1
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这是java手册的前五个文件,pdg格式
这是java手册的前五个文件,pdg格式-This is the first five manual document format PDG
- 2022-06-17 04:43:49下载
- 积分:1