格雷码转二进制的Verilog程序

de2-70 camera 亲测可以下载验证 直接下载使用即可

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)

本控制器与博世参考模型测试

使用VHDL编写数字蜂鸣器音乐，整个项目文件，可直接使用 (Use VHDL to write 1602led driver, the entire project file, and can be used directly.)

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

用xilinx ISE软件实现串口调试的程序其中，包含FIFO的一个IP核用于缓存数据

vivado入门使用介绍，初学者入门学习(vivado Instructional pdf)

数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)