混沌单用户csk调制仿真程序，计算了混沌调制的误码率性能

powerline communication 的 channel-powerline communication channel

S7-200之间网络通信读写数据的程序，包括通信口，数据速率，控制字等的设置。-S7-200 to read and write data between the network communication procedures, including the communication port, data rate, control words and other settings.

源代码展示了VC下命名管道的用法 详细代码示范命名管道的建立、通信、应用基本方法，思路清晰明了。

另外一个XML格式文件xsl，对soap的理解更深，有表头明细-another xsl XML format, the right soap deeper understanding, the first detailed Table

nrf2041,通讯的基本程序，是NRF公司提供的程序框架，是nrf编成的最终参考文档，在看懂了我上载的前几个文档以后，如果还有问题，那么只有这个文档能帮你了。-nrf2041, communication of the basic procedures that the company is NRF framework of the procedures, nrf organization is the ultimate reference document, I understand there are a number of documents, if there are problems, So this is the only document to help you.

虽然Windows下可视化开发工具如VC、Delphi、C＋＋ Builder等都有专用的定时器控件Timer，而且使用很方便，可以实现一定的定时功能，但最小计时精度仅为55ms，且定时器消息在多任务操作系统中的优先级很低，不能得到及时响应，往往不能满足实时控制环境下的应用。不过Microsoft公司在Win32 API函数库中已经为用户提供了一组用于高精度计时的底层函数，如果用户使用得当，计时精度可到1ms。这个计时精度、对于一般的实时系统控制完全可以满足要求。现将由C＋＋ Builder 4.0提供的重新封装后的一组与时间相关的主要接口函数（函数名、参数、功能与Win32 API基本相同）说明如下： -visual development tools such as Visual C++, Delphi, C++ Builder and others all have dedicated Timer timer control, but it is convenient. can achieve a timing function, but only the minimum time of 55 ms accuracy. Timer news and multi-task operating system in the low priority that is not to respond in a timely manner, often fail to meet the real-time control environment applications. However, Microsoft Corporation in the Win32 API function has been to provide the user with a group for high-precision the bottom was a time function, if the user is properly utilized, time accuracy can be a ms. Accuracy this time, and for most of the real-time control system can meet the requirements.

三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf

中文RFC文件，无需翻译，对学习很有帮助！

小灵通系统网关程序 -PHS system gateway procedures

想做AVR下移植UC／OS－II RTOS的朋友可以用这个教程来摆脱ICC编译器的单调界面，使写程序与改程序变得更加简单，方便-AVR wants to transplant under the UC/OS-II RTOS of a friend can use this course to shake off the monotony of ICC compiler interface, so that written procedures and the procedures to become more simple and convenient! ! !