Verilog 仲裁器

VHDL Programmes -2 for dumping on FPGA

说明：  I2C MASTER DESIGNED by Verilog

对于学习FPGA的同学来说仿真是必不可少的流程 但是仿真的方法signal tap是必须掌握的(For students learning FPGA simulation is an essential process but the simulation method tap signal is a must)

多频信号通过低通滤波器，使用Verilog语言进行设计，多频信号是正弦信号。

本模块是实现格雷码和二进制码的转换，并给出仿真测试文件(This module is to achieve the conversion of Gray code and binary code, and give the simulation test file)

它是一种算法，它是用来在超大规模集成电路的乘法2

它是为使用多个波纹的常规结构的 16 位进行选择加法器 verilog 代码执行加法器和多路复用器

AES加密算法verilog源码 This project is the hardware implementation of the  Advanced Encryption Standard with a key size of 128 bits. The implementation adheres to the FIPS-197 document which explains the same.The core can do both encryption as well as decryption.The documents aes_arch.doc and aes_tb_readme.txt give further details of the rtl implementation and test bench respectively. This code was written originally with 128 bit ports for both input and key but later converted to 64 bits each to save on i/o pins. It can be reverted back easily if one just changes the port widths and dispenses with the load signal in the top module and making approriate changes in process where load is used.Synthesis results have been included for Xilinx Spartan-3 device.The directory structure of the project is as under- AES128

this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal

CAN VHDL Code. Behavioral implementation of CAN bus interface.