This is a source code, the USB quite good, we hope to see down the download. , A

1个键有10种功能，带proteus访真文件。-A key with 10 function, with a true file proteus visit.

ATmaga128单片机TIMER1(16位定时器)程序 通过设计寄存器的值可以实现准确的定时信号输出-ATmaga128 single chip TIMER1 (16-bit timer) register through the design process can achieve an accurate value of the timing signal output

DMDD的嵌入式系统构件源代码-DMDD embedded system component source code

CSP封装技术,最新IC封装技术.--CSP packaging technique, the latest IC packaging technique.

proteus中PIC单片机仿真库文件。-Single-chip simulation in Proteus PIC library file.

fft，ifft运算，c语言程序设计，信号处理算法-ifft c program signal produce

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s3c2440，2410 的初始化汇编代码，一般用于在arm开发时用作无操作系统下的开发-2440init.s 2410.s

应用背景Abstract—Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive softcore for many-core research with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented

在嵌入式系统中对Lattice CPLD软件升级时所需的VME文件生成所需源代码。--Generate the VME file required for updating Lattice CPLD in embedded systems.