一个verilog的MP3解码项目

LDPC编译码，最新一代纠错码技术，自带校验矩阵，数据程序内带测试数据

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )

该源码用vhdl语言制作了一个简单的交通灯，方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)

my code be helpful for someone, and in fact, do not download it

verilog编写的GPS /BD基带逻辑代码，包含跟踪相关部分代码，有比较好的借鉴意义。

rc6 algorithm designed based on verilog and is verified

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

我们要提出新的 SRAM bitcell 以较少的功率消耗，读稳定性、 面积小于现有的施密特触发器基于 SRAM 和其他现有的设计，通过新的设计相结合的虚拟接地与读取错误减少逻辑。 可调滞回 CMOS 施密特触发器 磁滞 CMOS 施密特触发器设计策略研究了电压控制电流下沉和/或采购晶体管，迟滞窗口可以轻松地移动而不更改其宽度。对 ST 反馈逆变器进行了修改，晶体管被绊倒的逻辑 "0" 和 "1" 的逻辑。

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.