一个verilog的MP3解码项目

基于fpga的spi  master  testbench，             适合初学者

控制电话信令 完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)

这包括 verilog 代码为 4 位纹波计数器，编码在 Xilinx ISE 平台上。代码是经过测试，是好的。

说明：  基于EasyFPGA030的四位数字密码锁。(Based on the four-digit lock EasyFPGA030.)

一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)

在BASYS3上实现跑马灯的功能。第一LED交替闪烁；第二LED由左至右逐个变亮，再逐个变暗；第三LED由右至左逐个变亮，再逐个变暗；第四LED由两边逐个变亮，再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)

FPGA做VGA视频显示的详细资料，我找了很久才收集起的，有四篇文章，很有用(FPGA do VGA video display detailed information, I found a long time before they start collecting, with four articles, very useful)

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

an 16 bit ripple carry adder

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)