FPGA的串口通信verilog代码

使用verilog实现模六十计数即0-1-2-3-4-5-.......-59-0-1-2的功能。(Use Verilog to realize the function of the mode sixty count, 0-1-2-3-4-5-....-59-0-1-2.)

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

FPGA按键延时模块，产生key_value和key_flag 可直接例化调用(The key delay module of FPGA)

AL422B,FPGA写的控制时序。XIWANGDUIDAJIAYOUYONG(AL422B,timing of AL422b.)

这个代码主要展示了异步fifo的读的功能和写的功能(This code mainly shows the function of asynchronous FIFO and the function of writing.)

说明：  DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)

利用SCCB和FPGA实现视频采集的论文，对相关开发人员具有很强的参考价值！ (FPGA implementation using the SCCB and video collection of the papers, the relevant developer has a strong reference value ! )

FIR有限冲击响应下带通滤波器的构建及滤波器仿真（通过matlab和simulink两种方法实现）(FIR finite impulse response bandpass filter and filter simulation (via two methods matlab and simulink))

FPGA实现DDS波形发生器，多种信号的产生，(FPGA realization of DDS waveform generator to produce a variety of signals,)

CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)