D 触发器

低频数字式相位测量仪，数码管显示相位差，精度为0.1(Low frequency digital phase measuring instrument, digital pipe display phase difference )

说明：  AD6 中进行FPGA设计与仿真，很不错的资料哦(FPGA design and Simulation in AD6, very good data)

RS422通信程序，Verilog语言，此模块实现422通信功能(RS422 communication program, Verilog language, this module implements 422 communication function.)

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

台湾IC中心VHDL讲义，内容详细，适合IC前端设计参考(Taiwan s IC Center VHDL handouts, detailed reference design for front-end IC)

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)

Verilog语言的流水灯设计程序，对初学者很有用。(Water lights Verilog language design program useful for beginners.)

这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。 (This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)

基于FPGA的VGA控制器，可在屏幕显示彩色条纹(A vga controller based on FPGA)

基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)