ARM处理器：vivi bootloader，韩国直接生产过程中…

sunplus miniOS 文档-sunplus miniOS document

gprs协议实现-EDGE protocol

c51的 学习代码 主要是一些模块的 功能代码 希望初学者来学习-c51 learning the code is mainly the function of a number of code modules for beginners to learn hope

自己编的Freescale 32位微控制器MCF5223x系列的AD模块、PWM模块、QSPI模块综合应用程序（通过程序设定PWM模块，产生所需频率和占空比的脉冲，经过AD采样后，通过QSPI总线将处理数据传输到LCD上显示成脉冲的真实波形）。适用于学习Freescale微控制器的同学使用-Its own series of Freescale 32-bit microcontroller MCF5223x series of AD modules, PWM modules, QSPI module integrated applications (via the procedure set PWM module to generate the required frequency and duty cycle of the pulse, after AD after sampling, through the QSPI bus will process the data transmitted to the LCD display into the real pulse waveform). For students to learn the use of Freescale microcontrollers

正弦波表生成工具，可以设置不同的采样点和采样方式-Sine wave form generation tool, you can set up different sampling points and sampling methods

stm32的单片机实现的热敏打印机自检功能，可接收上位机数据

本系统分电压测量和信号产生输出两大部分，电压测量部分以模拟电路为主，配合放大模块、A/D转化模块、显示模块；通过凌阳单片机进行数据处理，在误差允许范围内显示测量电压值。信号产生以直接数字式频率合成器为核心，经过AT89S52对DDS芯片内部进行控制，使之输出标准正弦波形，利用编程实现频率预置、步进，达到电压输出频率的可调节步进。通过调试与测量完成了题目的基本部分和全部发挥部分的要求并有自己的创新。-Voltage measurement points of the system and the output of two major signals, voltage measurement circuitry to simulate the main part, with the amplification module, A/D conversion module, display module through Sunplus Single-chip data processing, in the range of error allowed shows the value of measuring voltage. Signal generated by direct digital frequency synthesizer for the core of the DDS chip AT89S52 after the internal control standards so that the output sine wave shape, frequency of use of pre-programming, step to the output voltage adjustable frequency step. Debugging and measurement, through the completion of the basic part of the topic and all the requirements to play a part and have their own innovation.

uclinux源码，已经再s3c44b0上移植成功！--Source code of uclinux. It was migrated to s3c44b0.

LPC2148 IIC驱动程序，驱动EEPROM-LPC2148

PLD编程笔记与补充 学习PLD的可以看看！共3个文件！-PLD programming notes and a supplementary study PLD that can take a look! A total of 3 files!