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java 是一个很好的网络开发环境。由于它是通过解释的方法,而不是通过编译的方法执行的,所以非常适合于网络平台。...
java 是一个很好的网络开发环境。由于它是通过解释的方法,而不是通过编译的方法执行的,所以非常适合于网络平台。-java is a good network development environment. Because it is through the explanation of the method, rather than through the methods of implementation of the compiler, therefore, very suitable for network platform.
- 2022-03-19 05:55:25下载
- 积分:1
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J2ee企业版服务器端高级编程(一)
有关各种企业级的编程
J2ee企业版服务器端高级编程(一)
有关各种企业级的编程-j2ee introduction and study zhi 1
- 2022-03-13 06:52:30下载
- 积分:1
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介绍C基本语法#,ASP.NET知识,有一个开发实例…
介绍C#基本语法,ASP.NET等知识,还有一个开发实例。-introduced basic syntax C#, ASP.NET knowledge, there are examples of a development.
- 2022-02-01 10:42:21下载
- 积分:1
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关于WIN的代码开发,介绍了关于windows 窗口的创建。
关于WIN的代码开发,介绍了关于windows 窗口的创建。-ok
- 2022-10-18 16:45:03下载
- 积分:1
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51 Microcontroller C language e
51单片机C语言学习的电子书(.exe格式)-51 Microcontroller C language e-book (. Exe format)
- 2023-03-31 18:50:03下载
- 积分:1
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everest的cjacker写的make使用心得
everest的cjacker写的make使用心得-everest
- 2022-08-07 08:50:30下载
- 积分:1
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分数/整数锁相环基础
fractional /integer PLL basics
- 2022-06-20 06:17:26下载
- 积分:1
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对ANSII进行了详细描叙,
对ANSII进行了详细描叙.
对ANSII进行了详细描叙,
对ANSII进行了详细描叙.-Of ANSII describes in detail, and describes in detail ANSII.
- 2023-01-31 14:05:04下载
- 积分:1
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core Java training materials 23 days long
core Java 培训资料
23天时长-core Java training materials 23 days long
- 2022-07-13 08:33:21下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1