alpha 处理器的 RTL实现

VHDL数字电路设计教程 乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)

Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)

ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)

说明：

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)

Verilog UART is written in this file

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)

Convert Roman numerals to integers