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关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

基于8位8核心MCU(FPPA)的RS232程序设计.-8 Based on 8-core MCU (FPPA) of the RS232 programming.

潜谈GIS的发展现状和发展趋势。同本问你应该会对GIS的开发有了进一步的认识-On the development of latent GIS status quo and development trends. With the question you should have further development of GIS awareness

< COM编程精彩实例>>电子书及其配套源代码

初学者的最佳选择-the best choice for beginners

正弦波源程序――――matlab 正弦波源程序----- Matlab source sine wave sine wave source

Borland,一个在微软的嘴中抢饭吃的公司,这本书详细地讲解了它的发展历程.-Borland, a company in the mouth, which would eat companies, this book explain in detail its course of development.

Java Project How to Write Small and Useful Programs

cisco密码恢复，详细描述cisco密码丢失恢复的过程

中国现代文学的典范-Modern Chinese Literature model