达芬奇系列嵌入式驱动开发程序实例

历变电源电路原理图己通过验证的希望对大家有所帮助-Calendar change power circuit schematic diagram has been authenticated

针对ARM优化过的FFT算法。其中20点，64点，80点的FFT算法。笔者试着加入了256点的FFT -for ARM optimized FFT algorithm off. 20 points, 64 points, 80 points of the FFT algorithm. I tried to join the 256-point FFT

这是一个完整的项目 C 计的使用 AVR.it 显示 C 的数目上 LCD.lanuage 是巴斯科姆 (基本) 你要注意程序的文件的所属到 EEPROM 内存和电路工作 properly.files 包括来源、 示意图、 多氯联苯的字符。

rtai-3.1-test3的源代码(Real-Time Application Interface )-rtai-3.1-test3 source code (Real-Time Application Interface)

how to use si labs microcontroller ADC

实现cpld和pc机之间的串口通信，PC机传送到CPLD的信息，CPLD传回到PC机-Via verilog language ，cpld can communcate with pc.

一个数字显示时钟的程序，用的是DS1302时钟芯片，用51单片机直接接口读取指令，有protues方针并且配合1602显示！-A digital display clock procedures, using a DS1302 clock chip, using 51 single-chip direct interface to read instructions, and have protues approach with 1602 show!

卫星调谐器 DBS TUNER The TA1322FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL.-The TA1322FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL.

nios软核的开发教程，详述了软核开发的一些细节-nios development of soft-core tutorial, detailing some of the details of soft-core development

基于CPLD的FSK信号发生器的设计.PDF-based CPLD FSK signal generator design. PDF