软件工程思想（好）

Universal Serial Bus Specification

随机信号课件 大家相互学习学习 有意见也请大家提出来 -Random signal courseware to learn from each other U.S. study has also asked people to put forward their views to

光接入网技术(电信新技术实用丛书), 光接入网技术(电信新技术实用丛书)-Optical access network technologies (telecommunications series of new technologies and practical), optical access network technologies (telecommunications utility of new technologies series)

☆☆网吧客户留言簿☆☆ 管理用户名和密码都是:admin 演示：http://www39.websamba.com/51rose/netbarbook/-Guest book ☆ ☆ ☆ ☆ cafe management user name and password are: admin demo: http://www39.websamba.com/51rose/netbarbook/

这个文件时在visual c++ 6.0下的MFC下的Directx 例子-The Directx example using MFC

c_c++技巧集-c_c skills Set

想要就给你好的TC哦-want gave the TC oh

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

详细介绍JPEG2000的编码原理和建议了FPGA实现结构-Detailed introduction JPEG2000 coding principles and recommendations of the FPGA structure

表格使用的常见问题及解决方法-forms of common problems and solutions