FTDI公司的应用程序和测试的FIFO

TMS320C6713的语音信号的FIR滤波，ccs开发环境。-TMS320C6713 voice signal FIR filtering, ccs development environment.

计算机视觉与嵌入式技术的结合，设计的监控系统，不错的论文。-Computer vision and embedded technology, the design of monitoring systems, a good thesis.

Dark Switch using 8051

3C90X驱动源码，应用于嵌入式操作系统。可以使用。--Source code of the driver for 3C90X. It could be used in embedded operating systems.

通过对计算机的组织与结构的分析，综合运用所学计算机原理知识，设计并实现较为完整的计算机，即模型机。它可以完成一般计算机的最基础功能，具备16条基本指令，以及4种寻址方式等。并且，计算机数据通路的控制将由微程序控制器来完成，CPU从内存中取出一条机器指令到指令执行结束的一个指令周期全部由微指令组成的序列来完成，即一条机器指令对应一个微程序。设计过程包括四个部分：㈠模型机硬件组成分析；㈡指令系统设计；㈢微程序设计；㈣上机实现，示范程序。- Through to the computer organization and the structure analysis, the synthesis utilization studies the computer principle knowledge, designs and realizes a more complete computer, namely molding machine. It may complete the common computer the most foundation function, has 16 elementary instructions, as well as 4 addressing ways and so on. And, the computer data path control will complete by the microprogram controller, CPU will take out a machine instruction from the memory a instruction cycle which finished to the instruction execution completely the sequence which will be composed by the microcode to complete, namely a machine instruction will correspond a microprogram. Design process including four parts: (1) Molding machine hardware composition analysis;

借助于SPCE061A的语音特色，我们开发出了这款语音控制播放器。该播放器不仅具有下一首、上一首、音量大、音量小和暂停等基本功能；同时配合SPCE061A的语音特色，实现语音控制功能。 语音控制小车的主要功能：

μC/OS-Ⅱ是一个完整的，可移植、固化和裁剪的实时多任务内核，是用ANSI的C语言编写的，包含一小部分汇编语言代码，使之可供不同架构的微处理器使用。-embedded operating system compiler environment hardware structure transplantation Case

目的：Ø 对使用 8051 微控制器的设计与研究交通灯信号系统。目标：Ø 对创建软件时间延迟Ø 写一个程序 trafficlight 系统Ø 组装、 下载和测试那些在目标板上。

8位LCD与8051系列控制器的接口。完美地适用于硬件和仿真。并且很容易连接更多的硬件和扩展代码..

应用背景Abstract—Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive softcore for many-core research with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented