L78XX(稳压).方面的资料，芯片资料叙述详细

VC++技术内幕源码-VC insider source technology

恩智浦公司lpc2000系列arm芯片的应用笔记。英文pdf资料。-NXP LPC2000 series arm chip company

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20 世纪70 年代以来,人们从工业过程的特点出发,寻找对模型精度要求不高而同样能实现高质量控制性能的方法,预测控制就是在这种背景下发展起来的。预测控制技术最初由Richalet 和Cutler 提出[1 ] ,它最大程度地结合了工业实际的要求,综合效果好,已经在理论和应用方面取得了显著进展,各种预测控制算法不断地产生并得到发展。预测控制算法具有三大本质特征:预测模型、滚动优化和反馈校正[2 ] 。它是不断滚动的局部优化,而非全局最优。预测控制的特点:建模方便 采用非最小化描述的离散卷积和模型,信息冗余量大,有利于提高系统的鲁棒性 采用滚动优化策略,使模型失配、畸变、干扰等引起的不确定性及时得到弥补,从而得到较好的动态控制性能 可推广到有约束条件、大迟延、非最小相位以及非线性等过程,对模型精度要求不高,跟踪性能良好,更适应于复杂工业过程控制。 -err

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

这个是由《Visual C++ 6.0实例教程》源代码教材里的一个关于简单处理文字内容(增加删除)的一个程序!都是自己编写,且已调试!-this is the "Visual C 6.0 tutorial examples" source code materials Lane on a simple text processing word content (increase delete) a procedure! they are prepared and have debugging!

2007 软件评测师考试试题及答案 pdf格式 -2007 software testing questions and answers pdf

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网络工程师历年试题以及答案2009年最新更新版-Network engineers over the years as well as answers to examination questions in 2009 latest update