24c02的c语言源代码，经测试可以运行，在atmel80C51运行无误

E-1330点阵液晶屏驱动程序-E- 1330 dot-matrix LCD driver

网络处理器例子程序1--Example 1 for network programming.

应用背景这是一个闹钟实现 ；功能一个数字闹钟在FPGA板。它是用Verilog语言，它是一个数字时钟程序相当成功地在FPGA开发板上运行。相比其他语言Verilog语言是更有用的和可靠的，这个计划包括了各种模块，你可以开发板上的模拟。关键技术时钟技术，连同连接的FPGA和下面的开关 同时，时钟开始。报警可以设置使用的FPGA板上的DIP开关设置。这是通过对应的DIP开关二极管。反不变当警报响起，蜂鸣器声音通过扬声器放大像。

利用该源代码可以实现在DE2的板子上进行USB画笔的实验-use of the source code can be achieved in the board Dictyophora USB brush on the experiment

这个芯片作的MP3播放器可是不错的!!!设计方案,全套-the chip for MP3 players but good! ! ! Program design, a full suite! !

AD7710的驱动程序，已调试通过--Driver program for AD7710.

在ADI公司网站找到一些一些关于AD73360的资料，或许有用-In ADI the company

GPS设计全攻略:GPS 应用基础 GPS 接收机原理图 选择GPS 方案所应考虑的几个方面-GPS design full Gonglue: GPS application infrastructure GPS receiver schematic diagram select GPS program should take into account several aspects of the

由 Xilinx 提供的 IIC 接口，使用 AXI interface。 Features ‧ AXI interface is based on the AXI4-Lite interface ‧ Master or slave operation ‧ Multi-master operation ‧ Software selectable acknowledge bit ‧ Arbitration lost interrupt with automatic mode switching from master to slave ‧ Calling address identification interrupt with automatic mode switching from master to slave ‧ START and STOP signal generation and detection ‧ Repeated START signal generation ‧ Acknowledge bit generation and detection ‧ Bus busy detec ‧ Fast mode 400 KHz operation or standard mode 100 KHz ‧ 7-bit or 10-bit addressing ‧ General call enable or disable ‧ Transmit and receive FIFOs - 16 bytes deep ‧ Throttling ‧ General purpose output, 1 bit to 8 bits wide ‧ Dynamic Start and Stop generation ‧ Filtering on the SCL and SDA signals to eliminate spurious pulses

处理器为s3c44b0,IIS播放,极好的资料，-processor s3c44b0, IIS broadcast excellent information,