verilog七段数码管

BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)

说明：  Verilog简易教程，或者说是讲义，清晰易懂，适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)

基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具， 各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。 (FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.)

基于FPGA的SD卡音频播放器 经过调试可以直接用，音质很好有MP3的所有功能(FPGA-based audio player, SD card can be directly used after debugging, good sound quality with all the features of MP3)

带时钟分频器的计数器的代码是用verilog编写的。代码是用verilog HDL编写的，完全可以合成，可以在FPGA上实现；

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

1． 了解Fir滤波器的设计原理和其线性特性； 2． 学会使用Verilog语言编程实现Fir滤波器的设计； 3． 熟悉quarters ii编程环境，并能够在此平台上实现文本设计、编译，并能够调用modelsim仿真出Fir滤波器的波形图； 4． 熟悉matlab软件的FDAtool工具和简单设计。

使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言(Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language)

MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)

用Verilog语言编写程序实现8比特约翰逊计数器(Write a program in Verilog language to implement the 8 bit Johnson counter.)