verilog七段数码管

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)

说明：  用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

基于FPGA的UART功能实现，包含四个模块，波特率产生，顶层，发送和产生模块。

利用Verilog实现了二维卷积的操作，输入特征图尺寸为7x7，卷积核尺寸为5x5，分别使用了折叠、脉动阵列行固定、脉动阵列权重保持三种硬件实现设计方法来完成二维卷积的设计。

Design FPGA in Labview

MICarrayWeights and MICarrayplot

基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)

用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)