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omnet++ Chinese user manual, discrete simulation of the essential handbook!
omnet++中文使用手册,离散仿真的必备手册!-omnet++ Chinese user manual, discrete simulation of the essential handbook!
- 2022-03-22 15:46:07下载
- 积分:1
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DW based study guides, from the most simple, basic school, and Beginners Guide t...
DW的基础学习教程,从最简单的,基本的学起,,初学者的必备学习教程-DW based study guides, from the most simple, basic school, and Beginners Guide to the essential learning
- 2023-07-09 15:15:03下载
- 积分:1
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ejb的使用指南,我见过的最好的EJB书籍之一,希望能得到大家的喜爱...
ejb的使用指南,我见过的最好的EJB书籍之一,希望能得到大家的喜爱-the use of the guidelines, I have seen the best EJB books, we hope to be the favorite
- 2023-07-13 01:05:03下载
- 积分:1
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电脑基本知识
电脑基本知识-Basic knowledge of computer
- 2022-03-26 06:29:06下载
- 积分:1
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Commonly used serial EEPROM memory chip 24c02 Chinese official information manua...
Commonly used serial EEPROM memory chip 24c02 Chinese official information manual, it was relatively easy to understand.-Serial memory 24c02 Chinese official information manual, it was relatively easy to understand.
- 2022-01-24 13:15:51下载
- 积分:1
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Beginning JavaScript
with DOM Scripting
and Ajax
Beginning JavaScript
with DOM Scripting
and Ajax
- 2023-03-17 20:30:05下载
- 积分:1
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高级J2EE 平 台 开发的电子书 2003 年9 月15日 出 版
高级J2EE 平 台 开发的电子书 2003 年9 月15日 出 版-senior J2EE platform of electronic books on September 15, 2003 published
- 2022-10-03 06:10:03下载
- 积分:1
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这基本上是一个原始图像,其中有汽车内饰的细节
This basically a raw image which has the details of the interiors of the car-This is basically a raw image which has the details of the interiors of the car
- 2023-08-27 17:35:03下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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自动控制原理简明教程 胡寿松版 ppt课件
本人近期教学所用课件!...
自动控制原理简明教程 胡寿松版 ppt课件
本人近期教学所用课件!-Hu Shousong automatic version of the principle of simple tutorial ppt teaching courseware I recently used software!
- 2022-06-21 02:28:07下载
- 积分:1