并行进，串行出的verilog源代码

VHDL Design of BCD to 7-segment decoder using PROM

sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)

说明：  中科院FPGA的课件！纯英文，比较简单，适合刚刚接触FPGA的小白！(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

hi this is an verilog codes

This design is an implement method of RAM wrapper, which can be used to connect peripheral device with SRAM, and realize Read-Write function base on the AHB bus protocol.

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

vhdl code for 8051 processor

verylog中的处理器设计代码。

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)