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linux嵌入式基础学习
linux嵌入式基础学习-embedded linux-based learning
- 2022-01-26 03:43:09下载
- 积分:1
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并行和分布式系统:集群和网格计算和“,”…
《分布式和并行系统:集群和网格计算》(英文版)
Distributed And Parallel Systems: Cluster And Grid Computing
介绍由澳大利亚和匈牙利组成的一个分布式和并行系统研究组织在集群计算和网格计算领域的最新研究成果。-"Parallel and Distributed Systems : clustering and grid computing "(English version) Parallel Distributed And Syste ms : And Grid Computing Cluster introduced by Australia and Hungary consisting of a sub- cloth-and the parallel system in cluster computing and grid computing is the latest research results.
- 2022-01-28 01:32:38下载
- 积分:1
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frasr200的win 版本源码(18.21),使用make文件,使用的vc版本较低,在我的环境下编译有问题! 很不错的分形程序代码!...
frasr200的win 版本源码(18.21),使用make文件,使用的vc版本较低,在我的环境下编译有问题! 很不错的分形程序代码!-frasr200 source version of the win (18.21), make use of documents and use the lower vc version, in my environment compiler problems! Very good fractal code!
- 2023-07-25 23:35:04下载
- 积分:1
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哲学
哲学-数理哲学导论[罗素]。高级程序员必修课-Philosophy- An Introduction to Mathematical Philosophy [Russell]. Compulsory advanced programmers
- 2022-04-27 14:33:52下载
- 积分:1
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计算机算法设计与分析_2主要分析算法以及分析,是本经典的电子书(中)...
计算机算法设计与分析_2主要分析算法以及分析,是本经典的电子书(中)-computer algorithm design and analysis of major _2 analysis algorithm and analysis, is the classic e-books (2)
- 2022-11-23 23:00:04下载
- 积分:1
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电子元件之通用电阻,标准电阻值选型表。内含所有常规电阻,阻值与封装。...
电子元件之通用电阻,标准电阻值选型表。内含所有常规电阻,阻值与封装。-Electronic components of the general resistance, standard resistance value selection table. Contains all conventional resistors, resistance and package.
- 2023-06-15 01:10:03下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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西门子S7200
西门子S7200-300应用论文,网上好不容易搞到的 很不错的哦-Siemens S7200-300 application papers, the Internet finally got a very good oh
- 2022-01-31 10:14:17下载
- 积分:1
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jScript手册
jScript手册-JScript Manual
- 2022-02-15 14:23:08下载
- 积分:1
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蔡智恒新书,<亦恕与珂雪>
蔡智恒新书,-蔡智恒new book, also forgive and Ke Xue>
- 2022-05-07 20:37:16下载
- 积分:1