《地理信息系统设计》书中的配套powerpoint文档

C语言算法大集合，包含10本书，全英文版的，对有学习英文版C语言的有很大帮助。-C language algorithms for large collections, including 10 books, all in English on the C language, learning English helps a lot.

游戏中的地图512种不同的图块拚成。实际应用中大约每个地图用到300种图块-Map game block of 512 kinds of different spell. About the practical application of 300 kinds of use of each block map

有别于一般教材的C入门书籍，从实用性出发。- Does not have to the common teaching material C basic books, embarks from the usability.

电动车控制器与充电器电路原理图 含多个品牌的充电器-Electric vehicle controller and the charger circuit diagram with multiple brands of chargers

高速光耦HCPL2530数据手册。速度为1M。双通道。-High Speed Optocoupler HCPL2530 Data Sheet. Speed of 1M. Dual-channel.

这是我最近一段时间编的一些弹片机的小程序,上面有大量的注释,一般都会看懂-This is a small program about single board computer writen by me recently, with a lot of comments, generally can be understood

Misc DVB standards including en50221 conditional access module standard

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

这是一个很好的教程-This is a good guide

想要学习java教本的同志们下来看看吧,希望有帮助-want java textbook learning comrades down to see it and hope for help