ReleaseNotes_CiscoPT5_2

侯俊杰的深入浅出MFC-Hou Junjie"s easy MFC

VB 文本语音 用于VB读汉字或英文字母，但由于比较简单，还存在一些却选择缺陷-Text to Speech VB

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

c++技巧-c++ skills

刘儒勋的运动界面追踪－VOF源代码-Mathematics, tracking the movement interface-VOF source code

Brushless Motor Drive Schematic & Data ebook

Osip开发者手册，是被翻译过的，中文版的，拿来共享一下-Osip development handbook, have been translated and the Chinese version, brought about sharing

一个用VHDL语言编写的译码器程序，希望学习的人能够下载学习。

ASP.net网页制作-ASP.net web

C++ Annotations Version 8.1.0~pre1 Frank B. Brokken Center of Information Technology, University of Groningen Nettelbosje 1, P.O. Box 11044, 9700 CA Groningen The Netherlands Published at the University of Groningen ISBN 90 367 0470 7 1994 - 2009 -C++ Annotations Version 8.1.0~pre1 Frank B. Brokken Center of Information Technology, University of Groningen Nettelbosje 1, P.O. Box 11044, 9700 CA Groningen The Netherlands Published at the University of Groningen ISBN 90 367 0470 7 1994- 2009