基于AHB总线的DMAC系统

FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)

EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)

LVDS并行数据传输，来自XILINX官网(LVDS Parallel Data Transfer)

半加器使用Verilog编码用于Xillinx

verilog语言编写的farrow滤波器的实现过程，供大家参考，谢谢。(Verilog language Farrow filter implementation process for your reference)

介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)

实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)

本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。

It is the FSM implemented in Xylinx 14.7 on FPGA