Verilog realize the DDS sine wave signal generator and frequency measurement mod...
于 2022-04-02 发布
文件大小:1.31 MB
0 323
下载积分: 2
下载次数: 1
代码说明：
Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
下载说明：请别用迅雷下载，失败请重下，重下不扣分！
发表评论
