木翼下载系统

Sundance FPGA 采集卡 Code-Sundance FPGA Acquisition Card Code

应用背景 SYFramework 此框架是泷涯自用，有的地方类似Yii 此项目基于Apache License 2.0开源 环境需求 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

EWB做的多功能数字钟 由振荡器输出稳定的高频脉冲信号作为时间基准，经分频器输出标准的秒脉冲，秒计数器满60向分计数器进位，分计数器满60向小时计数器进位，小时计数器按“12翻1”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒， 可发挥部分：使闹钟具有可整点报时与定时闹钟的功能。 -EWB done by the multi-function digital clock oscillator output stable high frequency pulse signal as a time reference. Frequency Divider output by the standards of seconds pulse, aged 60 seconds to counter-counter rounding, Counter-to-60-hour counter rounding, by the Counter-hour "12 over a" law count, Counter by the decoder to display; Counting errors school circuit can be used for schools, school hours, school seconds to play : The alarm clock can be made with whole point regular alarm clock and timer functions.

推箱子游戏,直得对游戏开发的朋友学习或参考.-Sokoban games, straight to the game developers have a friend learning or reference.

基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA

代码 matlab 的检测目标; 此方法已经是好在雷达系统

简易窗口隐藏源码 简易窗口隐藏源码 简易窗口隐藏源码 简易窗口隐藏源码

这是个通信录源代码-This is a recorded communications source code

模拟电路，答案3，最后一个了，希望能帮到大家-Analog circuits, the answer is 3, the last one, I hope to help you

ccs 2009 manual for pic comfile