ADC_Ctrl

说明：  平方环载波同步法FPGA实现的verilog代码(square loop carrier wave syn)

实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用(it is good ...)

说明：  基于fpga的函数发生器设计通过fpga实现正弦波输出(基于fpga的函数发生器)

说明：  实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)

ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)

FIFO is a First-In-First-Out memory queue with control logic that manages  the read and write operations, generates status flags, and provides optional  handshake signals for interfacing with the user logic. It is often used to  control the flow of data between source and destination. FIFO can be  classified as synchronous or asynchronous depending on whether same clock  or different (asynchronous) clocks control the read and write operations. In  this project the objective is to design, verify and synthesize a synchronous  FIFO using binary coded read and write pointers to address the memory  array. FFIO full and empty flags are generated and passed on to source and  destination logics, respectively, to pre-empt any overflow or underflow of  data. In this way data integrity between source and destination is maintained.  The RTL description for the FIFO is

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)

Design approach for VHDL and FPGA Implementation of Automotive Black Box using CAN Protocol

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )