FPGA 视频录制

说明：  一个8位RiSC单片机的VHDL代码， 具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)

自己写的_MIPS CPU，根据MIPS指令集设计，采用verilog编写，一步一步完善，结构简单清晰，可作为教学使用！        

這是一般通訊介面會採用的8B/10B 解碼, 應用在光纖通訊, Serdes上均有廣泛應用 /* Module Description:  This module implements a 8b10b decoder according to the original patent work  of Widmer and Franaszek.  It is a synchronous module with registers on the input  and output.  It takes in a 10-bit 8b10b encoded word, and outputs and 8-bit data  word and a control bit to indicate if the 8-bit output data is one of 12 special  K-codes.  */

采集外部设备的电压值，用FPGA内部自带的XADC(Collect the voltage value of the external device and use the internal XADC of the FPGA)

说明：  rgmii代码编写，实现rgmii接口功能，可进行参考设计(The rgmii code is written to realize the function of rgmii interface, which can be used for reference design)

ALTERA FPGA CLPD

PCI vhdl for Fpga designer to design PCI IP

使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)