FPGA 视频录制

C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)

LAB 9, Excercise for DE2 Altera

同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)

说明：  基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

格子玻尔兹曼方法模拟poiseuille流，半反弹边界，适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

用FPGA实现SPWM波输出，其中包含三角波和正弦波(With the FPGA realization of SPWM wave output, including triangle wave and sine wave )

基于AT89C51的密码锁（掉电可记忆密码）的程序(Based on AT89C51 lock (down to remembering passwords) program)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)