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关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

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QPSK解调端的代码，和上一个程序是对应的-QPSK demodulation side code, and a procedure is the corresponding

神经网络理论与MATLAB7实现 很详细 对学习神经网络很有帮助-Neural Network Theory and MATLAB7 to achieve a very detailed very helpful for learning neural networks

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基于嵌入式GIS开发应用，手持终端上的GIS应用

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LINUX设备驱动程序编写的一本好书，适合于初学者-LINUX device driver written a good book, suitable for beginners