描述了C++文件操作的操作方法 ios::app：　　　以追加的方式打开文件 ios::ate：　　　文件打开后定位到文件尾，ios:app就包含有此...

用 VISUAL C++ 设计WIN32应用程序-with VISUAL C Design WIN32 applications

创建特色按钮，vc6.0环境下开发，很有用啊-Button to create features, vc6.0 environment development, useful ah

很好用的文本留言程序.-good use of text messages procedures.

asp.net的入门书籍-Asp. Net book entry

用户名admin、密码123456可登录到管理员级别的用户界面。 用户名user、密码123456可登录到普通用户级别的用户界面 初始的家庭成员财务信息文件名为family，如要利用此系统进行家庭成员财务信息的管理，系统会提示用户输入家庭成员财务信息的文件名，则要输入此文件名，或输入管理员使用系统时新建的文件名。如删除该文件，则需在系统中调用相应的功能函数重新创建初始化文件。 初始的用户信息所在的文件名为yonghu，系统默认即为此文件名，不可删除。 -Username admin, password 123456 can log on to the administrator-level user interface. User name user, password 123456 can log on to the ordinary user-level user interface the initial members of the family financial information document, entitled family, such as to make use of this system of family members of the management of financial information, the system prompts the user to enter financial information of family members file name, will have to enter this file name, or enter the system administrator to use the new file name. Such as delete the file, then call in the system function corresponding to re-create the initialization file. User information where the initial document yonghu, that is, to this end the system default file name, can not delete.

是JSP电子图书-electronic books

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

串口通讯，可以用来进行串口通讯的事件-serial communications, can be used for serial communication events

3d图形学的一本电子书，内容涵盖了有关三地方面的很多问题-3d computer graphics, included a lot of context related to openGl

It is an production planning system