IIC总线Verilog实现（读写16为数据）

使用Verilog完成DS1302的驱动，工程已经经过测试，可直接使用。(DS1302 using Verilog complete drive, the project has been tested and can be used directly.)

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

verilog source code for SD card SLAVE DEVICE IP-Core

该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕(The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen)

Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)

一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)

说明：  一个使用VHDL进行正弦波信号产生的历程，非常有用。(A sine wave signal generator using VHDL for the course, very useful.)

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)