FPCA_彩灯控制器

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)

axi slave 模型，verilog描述，自己可以根据自己的设计适当修改。基本功能可能存在bug，不过是模型，大家可以自己稍作修改。

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)

基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)

说明：  基于altera fpga的fir IP核实现希尔伯特变换，有matlab仿真(Based on Altera FPGA fir IP core to achieve Hilbert transform, matlab simulation)

基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

基于FPGA的温度控制系统 VHDL 数码管显示温度 ds1820 温度报警(The temperature control system based on FPGA VHDL digital display temperature ds1820 temperature alarm)