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关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

用ＶＣ＋＋做的一个小程序，能简单实现托盘功能-To do with VC++ is a small program that can achieve the tray features a simple

无线通信经典书籍 无线通信经典书籍-Classic books on wireless communications,

微软公司出版的,有兴趣的朋友可以-Microsoft published

一个讲的不错的JBPM视频讲解,自己看吧，我没空写-jbpm

一个VC入门教程,感觉还可以,不知道大家上传过吧?-A VC Tutorial feeling can also be, I do not know everyone uploaded it?

graphics学习教程，学习c语言图形化的函数，掌握C的基本绘图方法-graphics learning tutorial, learn c language graphical functions, to master the basic method of drawing C

中断介绍，什么是中断，什么是软中断、硬中断，中断控制器，中断命令字，中断控制字。-Interrupted introduction, what is the disruption, what is the soft interrupt, hardware interrupt, interrupt controller, interrupt a command word, interrupt control word.

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汇编教程,解说详尽-Compilation of tutorial explain in detail .........................