通过VHDL语言的例子，FPGA的VHDL语言的原型（八）是

This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.-This tutorial explains how to communicate with IO devices on the DE2 Board and how to deal with interrupts using C and the Altera Monitor Program. Two example programs are given that diplay the state of the toggle switches on the red LEDs. The fi rst program uses the programmed I/O approach and the second program uses interrupts.

此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC) and the picture element positional information; Another receive picture element positional information, and output color signal. Like this is advantageous for carries on the graph to revise, simultaneously is also easy to realize

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)

modelsim的一个非常好的教程，有程序源码，PPT，word教程-ModelSim

自己编写的，浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)

基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)

AHBtoAPB设计基于AMBA总线协议的APB Bridge设计(AHB to APB designThe AHB to APB bridge interface is an AHB slave. When accessed (in normal operation or system test) it initiates an access to the APB.)

基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of