无线通信FPGA设计的例程源码

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

Design FPGA in Labview

these are the source codes for the book " 100 power tips for FPGA designers"

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

cvery high compatibles for quartus

数字滤波器组。包含matlab程序和word说明。通过一个低通数字滤波器和多个带通数字滤波器组合成一个滤波器组(Groups of the digital filter. Contains matlab program and word description. Through the combination of a low pass digital filter, and a plurality of band-pass digital filter into a filter bank)

VHDL CODE FOR SQUARE WAVE GENERATOR

完成RS（5，3）编码程序，运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)

该模块依据输入的温度，来自动调整PWM输出的占空比，从而进行CPU散热风扇的智能调速，温度需要上层软件往该模块中下发。