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AES加密算法

于 2022-03-15 发布 文件大小:189.88 kB
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128位的AES加密算法、可以在FPGA上实现。利用硬件描述语言Verilog实现。各个模块都有,行变换、列混淆、轮密钥加变换、密钥扩展,并且有说明文档PDPF格式的。有完整的测试程序Testbench。特别适合研究AES加密算法的爱好者。

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