8 x 8 乘法器

在Nexys4开发板上实现一个时钟的显示，利用了视觉暂留的功能实现数码管的输出，但因为时间问题，小时的位数只设计了一位，需要两位的话加一位即可。

FAST HADAMARD TRANSFORM VERILOG FOR IMAGE PROCESSING

使用FPGA实现三相直流无刷电机换相，该程序可以使用(Use FPGA to realize the three-phase brushless DC motor commutation, the program can use)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)

说明：  FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)

一個紅外線感測電路的設計，是經由opa來設計。(An infrared sensing circuit design, is designed by opa.)

Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)