8 x 8 乘法器

用FPGA实现 VGA显示的图像显示控制器设计 用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design Using VHDL hardware implementation is colored stripes appear above the screen)

RS编码器的fpga实现，有TESTBench(RS encoder to achieve the fpga, and TESTBench)

ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

vc707 board getting started guide

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

异步FIFO的实现，很经典的三段式状态机的写法。(The realization of the asynchronous FIFO, very classic three-step writing state machine.)

基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)

说明：  电路四倍频算法，具有去毛刺，整形功能，方向及计数(Circuit quadruple frequency algorithm, with deburring, shaping function)