8 x 8 乘法器

基于ep4ce22的verilog串口程序，可发送24bit，希望能给大家提供帮助。

直接序列扩频系统的收发系统，可以进行参数配置(this is a Verilog program )

是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)

基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)

AD4003的Verilog程序，验证有用(Verilog code for AD4003)

根据软件无线电的思想，提出了一种新颖的数字信号处理算法，对QPSK信号的相位进行数字化处理，从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差，用数字锁相实现收发端载波的同步，在频偏较大的情况下，估算频偏的大小，自适应设置环路的带宽，实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台，并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点，符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)

我们按照应用的需求来定义计算机，本文介绍一个非常简单的CPU的设计，它仅仅用来教学使用的。我们规定它可以存取的存储器为64byte，其中1byte=8bits。所以这个CPU就有6位的地址线A[5：0]，和8位的数据线D[7：0]。 　　我们仅定义一个通用寄存器AC（8bits寄存器），它仅仅执行4条指令如下： 　　Instruction 　　Instruction Code 　　Operation 　　ADD 　　00AAAAAA 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

4tap FIR filter in verilog code

说明：  在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal generated by the M sequence generator, through the AD module on the oscilloscope display module, oil DA demodulation operation in the same block experiment board, the signal generation control LED lights off, and the modulated output signal displayed on the oscilloscope at the same time, and compared.)