gsm model..........it i sgreat useful........check i t out

这是有关NS2中802.16的代码的文章-This is the NS2 in the code article 802.16

一个很好的Icq网络聊天工具,非常好.-a good Icq Internet chat tools, very good.

一款可以检测USB通信数据的工具及其代码，里面有三种方式（报告、特征报告和读写文件的方式）来测试HID通信PC TO HOST AND HOST TO PC 的数据，我在模拟HID接口时受益非浅。在XP VS2003 环境下面测试通过！这里希望能达到抛砖引玉的作用！-one can detect USB data communication tools and code, which has three methods (report, Feature reports and documents through the reading and writing) to test communications HID PC TO HOST AND HOST TO PC The data, I simulated HID benefited greatly from the interface. In XP VS2003 below the test environment! Here hope to get feedback from the role!

This paper discusses the establishment and relevant accomplishments of a simple facility used for students learning aids based on the Keplerian Orbit parameters. Three major areas in Orbital Mechanics are discussed in this paper, Orbit of a satellite, Field of View of a satellite and Constellation of Satellites. -This paper discusses the establishment and relevant accomplishments of a simple facility used for students learning aids based on the Keplerian Orbit parameters. Three major areas in Orbital Mechanics are discussed in this paper, Orbit of a satellite, Field of View of a satellite and Constellation of Satellites.

文章中分析了OFDM系统的频谱利用率，研究了OFDM系统中的信道判决反馈均衡问题-Article analyzes the spectral efficiency of OFDM systems to study the OFDM system channel decision feedback equalizer problem

Win32串口编程技术,vc++环境下，可以帮助你在短时间内理解串口编程，当然最好的方法还是看msdn.-Win32 Serial Programming technology, vc circumstances, can help you understand in a short period of time serial programming, of course, the best way to watch msdn.

对于QPSK通信系统的蒙特卡洛仿真-monte carlo simulation on the QPSK communication system

一个原始sock的数据网络通讯程序。-an original sock data network communication process.

rs232 verilog code inclouding of TRX and testbench. This zip file contains the following folders: verilog_source  -- Source Verilog files:  uart.v   -- top level file  txmit.v  -- transmit portion of uart  rcvr.v   -- receive portion of uart -- Source Verilog files:  txmit_tf.v -- testbench for transmit portion of uart  rcvr_tf.v  -- testbench for receive portion of uart  

Text of article "draft-kamath-pppext-peapv0-00.txt"