Verilog_HDL时序篇 教程及代码

说明：  Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

无SDRAM的PCI采集,给出PCI采集的FPGA程序，桥芯片也为PLX9054，已验证通过(No SDRAM, PCI capture, given FPGA PCI acquisition program, bridge chips for PLX9054, has been verified by)

说明：  verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)

本文研究的IIC总线控制器具有如下特征 1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。 2.多主操作 3.软件可编程时钟频率 4.时钟拉伸和等待状态生成 5.软件可编程确认位 6.时钟同步设计 7.仲裁中断丢失，自动转移取消 8.开始/停止/重复启动检测/确认生成 9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics. 1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18]. 2. Multiple Main Operations 3. Software programmable clock frequency 4. Clock stretching and waiting state generation 5. Software Programmable Confirmation Bit 6. Clock Synchronization Design 7. Loss of arbitration interruption and cancellation of automatic transfer 8. Start/Stop/Repeat Start Detection/Verification Generation 9. Bus busy detection)

FPGA驱动VGA在电脑显示屏上显示彩条                                                                                                                        附有注释

针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)

DDS的VHDL程序，相当好，值得下载，共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)

在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)

数字时钟的Verilog程序，用quartus打开就能使用，可以用做课程设计、电子设计等使用

基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，基于Verilog的CRC算法源代码，