完整的网站设计的毕业论文及代码，可以作为毕业论文使用，很清晰的设计...

本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.

verilog hdl verilog hdl verilog hdl -verilog hdl

缓存设计详解,对缓存在web应用上的设计做了比较全面的阐述.-Cache design Xiangjie, to the cache in the design of web applications have done a more comprehensive elaboration.

IIC规范中文协议,内容比较全,比较新,为你的系统设计提供参考-IIC standardize Chinese agreement, the entire contents of comparison, the relatively new system design for your reference

有源RFID系统读写器和标签的设计方案和程序流程图。-Active RFID reader and tag system design and program flow diagram.

　介绍了一种运用DSP (数字信号处理器)控制的基于以太网传输的低成本高音质语音 监控系统,该系统主要由语音采集模块和语音传输模块组成。-Introduced the use of a DSP (digital signal processor)-controlled, low-cost Ethernet-based high-quality transmission of voice control system, the system mainly by the voice acquisition module and voice transmission module.

this is rar files useful for the project beginers

a general informaiton about vsworks

操作系统资料，算法-operating system information, the algorithm

看名字拉-saw the name Rafah