H.264解码Verilog

半带滤波器，工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)

写一个单周期处理器运行一段mips指令，并包含mips指令转汇编码的程序(Write a single cycle processor to run a section of MIPS instruction)

轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言(verilog language manuals, and the other enjoying VHDL hardware description language 1)

16b20b encoder and decoder

Vhdl design z80 for altera users

利用ISE工具，完成对v6系列的FPGA上PCIE以及DMA数据测试仿真，可以通过编译产生仿真波形，也可以根据自己的开发板烧录到自己的板子上

THIS IS A SOURCE CODE FOR LIFT IN VHDL LANGUAGE

说明：  sd_sdram_lcd 是读取SD卡中的数据，然后通过LCD显示(It is to read the data in SD card and display it by LCD)