Wireless transceiver modules for nRF5E5, 905 initialization, send and receive se...

磁盘仿真存储系统，用文件来虚拟磁盘，可以建立文件夹或者文件，并对它们进行操作-good

2维FDTD的MATLAB代码，TM波代码-2 dimension FDTD program (TM mode) All boundaries are perfect conductors. // For Visualization of the field, I use PGPLOT which is available as port // (for FreeBSD) or binary package (for Debian Linux). // (1) In FreeBSD, compile with // gcc-o fdtd fdtd.c-I/usr/local/include-L/usr/local/lib-L/usr/X11R6/lib // -lcpgplot-lpgplot-lg2c-lX11-lm // (2) In debian Linux, complile with // gcc-o fdtd fdtd.c-lcpgplot-lpgplot-L/usr/X11R6/lib-lX11-lpng // -lz-lm

在这个项目中，我们使用avr控制器atmega162远程控制设备。它包含电路，给定主题的源代码。要完全了解红外遥控器的基本知识，请点击链接。

template实例 可以测试编译器支持的标准程度，g++和borland c++编译器都能通过-template examples can test the compiler to support the standard, g and borland c compiler can be accessed through the

俄罗斯方块-Tetris

归并和快速算法比较-merging and fast algorithm

使用函数实现简单的八位处理器 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个可以进行两个八位操作数四种操作的简单处理器； 2. 工程在project文件夹中，双击mpc.ise文件打开工程； 3. 源文件在rtl文件夹中，mpc.v为设计文件，mpc_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择mpc_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-The use of a simple function to achieve the eight-processor software development environment: ISE 7.1i simulation environment: ISE Simulator 1. This example through the ISE Simulator tool to achieve the realization of a two operand four of eight simple processor operation 2. works in the project folder, double-click to open the project file mpc.ise 3. rtl source file in the folder, mpc.v documents for the design, mpc_tb.tbw is the simulation waveform files 4. to open a project, a browser in the works Select device mpc_tb.tbw, double-click in the Process View in the " Simulation Behavioral Model" option, to carry out acts of simulation, simulation results can be obtained.

A simple spim assemply example code on creating a list and calling functions

HDLC在通讯设备中占有重要地位，本文件提供了完整正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值-HDLC in the communications equipment plays an important role, this document is to provide a complete hardware HDLC correct logic design! Design and learning have a reference value

A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.