FEC2/3加解码

文本加密和解密

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one.  The AES Decryption Core for FPGA implements the decryption portion of the AES (a.k.a. Rijndael) algorithm described in the FIPS-197 specification. Key lengths of 128 / 192 / 256 bits are supported, each with a separate instantiation wrapper. Since the core is designed to take advantage of LUT6 based FPGA archit

AES算法主要包括三个方面：轮变化、轮数和密钥扩展。本文以128为例，介绍算法的基本原理；结合C语言，实现高级数据加密算法AES（AES-128）。-AES algorithm mainly includes three aspects: round of changes, round number and key expansion. In this paper, 128 for example, introduce the basic principles of algorithm combination of C language, the realization of advanced data encryption algorithm AES (AES-128).

DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm

内容:基于jdk1.4的加密算法的具体实现，算法包括MD5,SHA-1,DES,DESede,RSA等-: jdk1.4 based on the encryption algorithm to realize the algorithm including MD5, SHA-1, DES, DESede, RSA, etc.

简单加密工具原程序-simple encryption tools original program

RSA加密算法在VB中的实现.可以更好的了解RSA加密算法.-RSA encryption algorithm in VB realized. To better understand the RSA encryption algorithm.

包括 LIB、DLL 加密模块 各种语言调用加密模块的例子程序等-including LIB, DLL encryption modules in various languages called encryption module examples procedures

implementation of rijndael furious algorithm to encrypt and decrypt information

vc++6.0下的md5源程序-vc 6.0 source of md5