des加密算法的vhdl和verilog源程序

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

一个用 verilog 实现的对FPGA串口进行控制的，串口控制器源代码(A serial port of FPGA is controlled by verilog. The source code of serial port controller)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

这是Uwe Meyer-Baese先生的代码，我有全部的代码，如果有人需要的话，可以联系我。haozix521@gmail.com

a power point presentation presenting how to impliment EMF and GMF with DDS

ad9361 matlab驱动代码，运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)

应用背景Project: A Wishbone Controlled Real--time Clock Core Purpose: Implement a real time clock, including alarm, count--down timer, stopwatch, variable time frequency, and more.关键技术基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。

GE PCI5565 PMC5565 PCIE5565反射内存网数据中断接收程序 接收中断 反射内存网 VMIC5565反射内存卡 实时仿真技术 PCI5565PIORC-110000(GE PCI5565 PMC5565 PCIE5565 reflective memory network data interrupt transmission program VMIC5565 reflective memory card real-time simulation technology)

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)