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ADS_CodeWarriorIDEGuide
ADS_CodeWarriorIDEGuide
- 2022-02-24 19:05:50下载
- 积分:1
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这是一个指纹识别系统的源代码,用vc编写的,效果不错呀
这是一个指纹识别系统的源代码,用vc编写的,效果不错呀 -This is a fingerprint recognition system source code, prepared by the vc used, the effect good game
- 2022-03-03 18:59:19下载
- 积分:1
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M.加斯特
M.Gast - 802.11 Wireless Networks The Definitive Guide. 2nd edition. 2005.chm-M.Gast- 802.11 Wireless Networks The Definitive Guide. 2nd edition. 2005.chm
- 2023-02-24 09:30:06下载
- 积分:1
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Internet_program_JAVA&HTML 需要的人看看吧
Internet_program_JAVA&HTML 需要的人看看吧-Internet_program_JAVAHTML those who need to see it
- 2022-02-01 07:38:15下载
- 积分:1
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这是本很好的电子书籍,很经典的学习协议的教材
这是本很好的电子书籍,很经典的学习协议的教材-this is the good e-books, the classic textbook learning agreement
- 2022-08-23 17:28:45下载
- 积分:1
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孙鑫老师VC++的视频教学!(第一章,已转化为多个FLASH文件,高质量)VC++入门必须了解的内容,Windows程序运行原理及程序编写流程,窗口产生过程,句...
孙鑫老师VC++的视频教学!(第一章,已转化为多个FLASH文件,高质量)VC++入门必须了解的内容,Windows程序运行原理及程序编写流程,窗口产生过程,句柄原理,消息队列,回调函数,窗口关闭与应用程序退出的工作关系,使用VC++的若干小技巧,stdcall与cdecl调用规范的比较,初学者常犯错误及注意事项.-Xin Sun Video VC teachers teaching! (The first chapter, has been translated into more than FLASH document, high quality) VC entry must understand the content, procedures Windows operating principle and procedure of the preparation process, window selection process, handle principle, Message Queue, a callback function, the window is closed and application procedures to withdraw from the working relationship The use of a number of small VC skills stdcall and cdecl calling norms, Beginners often make mistakes and tips.
- 2023-08-02 18:50:16下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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在terenaki西方学院技术评估。
the assessment of western institude technology at terenaki.
- 2022-02-25 00:22:56下载
- 积分:1
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神经网络源码!希望对大家有一定的帮助,以后会继续上传
神经网络源码!希望对大家有一定的帮助,以后会继续上传-neural network source! We hope to have some help, it will continue to upload
- 2022-03-18 09:15:15下载
- 积分:1
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详细讲述了通信电子线路的基本原理和设计要领,是不可多得的资料...
详细讲述了通信电子线路的基本原理和设计要领,是不可多得的资料-Detailed account of the communication the basic principles of electronic circuits and design essentials, is a rare data
- 2023-06-06 04:15:07下载
- 积分:1