Siemens Industrial Communication Guide Book CD

一维条件下用FDTD 计算模拟一脉冲进入有耗介质E场的变化。-1D FDTD simulated E field changes using a pulse hitting the dielectric medium .

这是s7200用于学习的教程，是以幻灯片方式的教程,容易学习-This is the tutorial for learning s7200 is way slide tutorial, easy to study

三级材料，可以参考。-three materials, reference.

Person-to-person realtime IP communications, like presence, VoIP and video applications, offer clear benefits for the enterprise as time- and money-savers. Unified functionality is now available, where all of the above are integrated into one streamlined application and interconnect with other networks. This creates a very important business tool and usage is increasing.-Person-to-person realtime IP communicat ions, like presence, VoIP and video applications. offer clear benefits for the enterprise as time- and money-savers. Unified functionality is n ow available, where all of the above are integrated into one st reamlined application and interconnect with o ther networks. This creates a very important bu siness tool and usage is increasing.

rfc2326中文文档,即RTSP(Real Time Stream Protocol)中文文档，学习和开发流媒体协议(rtsp)软件的圣经-rfc2326 Chinese document, that is, RTSP (Real Time Stream Protocol) Chinese documents, learning and development of streaming media protocol (rtsp) Bible software

Some tuning techniques covered in the emJava Performance Tuning-em book

关于名企面试的一些资料,里面包含了大量的面试题目和解析。-a pdf about interview

概观C++程序设计语言-overview C Programming Language

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

局域网速查手册，全面介绍局域网的各种技术参数。-LAN Quick Fact Manual, a comprehensive description of the various technical parameters of the LAN.