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介绍Linux内核结构的书籍。适合初学者使用。
介绍Linux内核结构的书籍。适合初学者使用。-Some introduction about linux and unix for beginners.
- 2022-08-20 02:49:10下载
- 积分:1
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很好的 东西 清华大学出版的数据结构课后习题详解
很好的 东西 清华大学出版的数据结构课后习题详解-Tsinghua University, published a good thing the data structure after-school Exercise Xiangjie
- 2023-08-24 09:40:04下载
- 积分:1
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java 入门
java 入门-java entry
- 2022-10-26 20:20:03下载
- 积分:1
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scjp的复习资料,SUN的四套测试题!
scjp的复习资料,SUN的四套测试题!-scjp review of the information, SUN that the four sets of tests!
- 2022-04-24 16:33:15下载
- 积分:1
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我看到许多论坛的朋友, 寻找 中文的javaAPI, 无奈sun没有提供中文的,这是SUN对中国程序员的轻视,有日文,为什么不能有中文,小日本为什么不用看英文。...
我看到许多论坛的朋友, 寻找 中文的javaAPI, 无奈sun没有提供中文的,这是SUN对中国程序员的轻视,有日文,为什么不能有中文,小日本为什么不用看英文。希望对大家学习java提供方便。-I see many friends in the forum, the Chinese find javaAPI Unfortunately, the Chinese do not provide sun, it is Sun programmers to China lightly, Japanese, why not Chinese, the small Japanese Why not look at the English. We hope to facilitate learning java.
- 2022-03-18 03:48:24下载
- 积分:1
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用于解离散对数问题的 商科斯算法,用c++编译的,可以实现
用于解离散对数问题的 商科斯算法,用c++编译的,可以实现-shanks
- 2022-02-13 17:45:13下载
- 积分:1
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本程序ds_cdma仿真的原理,直接可用,是乐…
本程序仿真了DS_CDMA的原理,直接可用,是学习CDMA的很好的教程-This procedure DS_CDMA simulation of the principle, directly available, is to learn from the good CDMA Tutorial
- 2022-03-01 02:12:16下载
- 积分:1
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用于ARM板上开发的环境ADS1。2的详细介绍,对于初学ARM开发很有好处...
用于ARM板上开发的环境ADS1。2的详细介绍,对于初学ARM开发很有好处-ARM board for the development of the environment degenerate. Detailed description of the two, for beginners it is very advantageous to the development of ARM
- 2022-05-20 03:46:41下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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精通NetBeans光盘源代码,很好 的资料
精通NetBeans光盘源代码,很好 的资料-CD-ROM master NetBeans source code, very good information
- 2022-03-13 19:57:08下载
- 积分:1