软件界面设计规范，适合学习软件设计的初学者

应用背景Abstract—Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive softcore for many-core research with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented

HPI与PC相通信的源代码 喜欢DSP的爱好者快来看看吧-HPI communication with the PC equivalent of the source code like DSP lovers Come see Look here

TMS320VC5416 DSK原理图.使用很方便，很好的资料-TMS320VC5416 DSK schematic. Very easy to use, very good information

ISP1582 原理图-ISP1582 Schematic

ucOS+minigui开发详细资料，非常实用-ucOS+ minigui ???详???柿??????实用

基于1-W器件的软件保护技术的研究，为了有效保护软件作者的知识产权，可以根据用户所用机器的硬件信息产生注册码，并在软件中对某些先进或常用功能进行限制，如果用户要使用其全部功能，必须将软件采集的有关硬件信息反馈给开发者，并交一定的注册费可获得该软件在自己机器中的注册码，才能正常使用。-Research of Software Protection Technology Based on 1-W Device

赛程计时采用倒计时方式，全场比赛48分钟，比赛开始，声光提示并启动时钟计时。在计时显示模式下：数码管前两位显示分钟，后两位用于显示秒钟。为满足比赛过程中，特殊情况暂停、更换球员暂停、战略性暂停，计时器设置有SW3暂停按键，按下按键计时器停止计时， 蜂鸣器叫一声，提示比赛暂停。再次按下按键，蜂鸣器叫一声，提示比赛重新开始，时钟计时继续。在比赛过程中任意时刻，按下SW6切换到比分显示模式：考虑到开发板资源，数码管前两位显示A队得分，后两位显示B队得分，最大计分为99，基本能够满足比赛计分要求。按键SW5控制A队得分，SW4控制B队得分。再次按下SW6重新切换到计时显示模式。需要注意的是在比分显示模式下计时并未停止。比赛共48分钟分为两大节，四小节；每一小节结束蜂鸣器报警提示，时钟计时暂停；每一大节结束蜂鸣器报警、计时暂停，中场交换比赛场地时，数码管交换甲、乙两队比分的位置。

详细介绍了WinCE系统下的媒体播放软件及其源码。-WinCE system, described in detail under the media player software and its source code.

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基于AT91SAM7SE512cpu使用SDRAM的例子，编译工具是IAR4_31A-AT91SAM7SE512cpu based on examples of the use of SDRAM, the compiler tool is IAR4_31A