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统计学习算法中的一种改进,它延伸出来的方面包括了很多的方面...
统计学习算法中的一种改进,它延伸出来的方面包括了很多的方面-Statistical learning algorithms in an improvement, it extends out include a lot of aspects of
- 2022-03-12 18:25:07下载
- 积分:1
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MODBUS 规范
PI_MBUS_300 .pdf
国家标准
MODBUS 规范
PI_MBUS_300 .pdf
国家标准-MODBUS specification PI_MBUS_300. Pdf National Institute of Standards
- 2022-11-01 08:50:02下载
- 积分:1
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Wrox.Professional.ASP.NET.2.0.Server.Control.and.Component.Development.Aug.2006,...
Wrox.Professional.ASP.NET.2.0.Server.Control.and.Component.Development.Aug.2006,用户自定义空件开发-Wrox.Professional.ASP.NET.2.0.Server.Control.and.Component.Development.Aug.2006, user-defined pieces of the development of space
- 2023-05-23 01:20:03下载
- 积分:1
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minigui编程指南,提供minigui开发的基础知识
minigui编程指南,提供minigui开发的基础知识-Programming Guide minigui provide the basis for the development of knowledge minigui
- 2022-04-23 23:31:39下载
- 积分:1
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c语言的常用函数以及一些小游戏代码,如文曲星小游戏、五子棋游戏等...
c语言的常用函数以及一些小游戏代码,如文曲星小游戏、五子棋游戏等-commonly used functions and some game code of c language ,
- 2023-06-20 23:25:03下载
- 积分:1
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ASP.NET 2.0 (c#) +AJAX 实现的公交查询系统,实现了站对站,路线,站对线查询...
ASP.NET 2.0 (c#) +AJAX 实现的公交查询系统,实现了站对站,路线,站对线查询-ASP.NET 2.0 (c#)+ AJAX realize Bus Inquiry System to realize the station stops, routes, points on line inquiry
- 2022-09-12 13:05:03下载
- 积分:1
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XSL语法详细参考手册,XML设计者的理想教材
XSL语法详细参考手册,XML设计者的理想教材-XSL detailed grammar reference manual, XML designers the ideal material
- 2023-01-31 09:15:04下载
- 积分:1
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The classic C language books, in
经典的C语言书籍,深入了解C的绝佳途径,对c的各个方面都有深入讲解-The classic C language books, in-depth understanding of C, an excellent means for c-depth briefing on the various aspects
- 2022-08-07 17:41:25下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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java 建模的书,结合UML讲解面向对象的设计
java 建模的书,结合UML讲解面向对象的设计-modeling, UML on the combination of object-oriented design
- 2022-03-29 09:51:44下载
- 积分:1